Thursday 12 April 2012

When to use signals and variables in VHDL

First let's see the purpose of a signal and a variable,The signals are used as a wire acting as a communication (conveying event information ) between design components ,so to put simply we use signals when we want to connect together blocks just like a wire between them.
The variables on the other hand are used for computation so you can roughly imagine a register whenever you use one ,And the most subtle distinction between the two is how they behave when used in a process.

Before seeing that let's understand why exactly do we need a process ?

A process is something like a wrapper that allows all the statements inside it to be executed sequentially that's one after the another.and those statements outside the process block execute concurrently.

Thus if we have  a = expression(b,c,d);

lets say we assign to a the result of the expression involving b,c and d now since all the parameters in vhdl will eventually mapped to hardware signals ,the expression will be evaluated whenever there is a change of signal status involving b,c and d or whenever either of b,c or d changes then the particular statement
a = expression(b,c,d);
gets executed so what if the program is something like

a1= expr(b,c);
a2 = expr (b,e);
a3 = expr (c,e);

so lets for example say signal b changes its state then statement a1 and a2 will get evaluated concurrently or simultaneously.

So we need a mechanism to prevent such concurrency depending on certain programming paradigms for which we use process whenever we need such a scenario.

The process expects a sensitivity list which is a list of signals specified to it and the process sleeps(sort of) until there is a change in signal status in its sensitivity list or the occurrence of an event which causes the signal to change its state will lead to waking up the process,so once the process is active then all the statements inside it will execute (yes!) sequentially.

But (Ahh) there is yet another subtlety and more often a wrong usage of variables and signals inside here causes error .


so for example if  v,v1 and so on are variables and s,s1 are signals
then inside a process if we use


lets say s ,s1 v and v1 are all type integer

and say s=0 and s1=0 v=0 and v1=0 initially
process(s,s1)
{
s1<= s+1; -- instruction executed but not assigned
s<=s1; -- s still has its old value
s<=s+1;
v:= v1 +1; -- instruction executed with immediate assignment
v1:=v+1;
}

So what are v ,v1 and s,s1 ? note that v,v1 are variables and s,s1 are signals


so what are the end values of each parameter ?
is s = 2 ?
whoa hold it right there,the statements are executed sequentially but the assignments to the signals happen when it exits the process but the variables inside the process is quite immune to this effect thus


lets see the values after the end of process block
s1=1
s=1
v=1
and v1 is 2

we see here that the variables are assigned immediately but the signal assignment only occurs once the process ends

And hence in all the signal assignment effectively takes the last expression which was assigned to it.